View ML87V2104_542624.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

OKI Semiconductor ML87V2104
GENERAL DESCRIPTION
PEDL87V2104DIGEST-01
Issue Date: Jan. 20, 2003
Preliminary
Video Signal Noise Reduction and Field Rate Conversion IC with a Built-in 4M Bit Field Memory
The ML87V2104 consists of a 3-port type (1 input port and 2 output ports) 4.4 Mbit (960 x 288 x 16bits) field memory and logic circuits for signal processing and memory control. The device can reduce field-recursive noise. Noise reduction auto mode can be set by detecting the noise in the vertical blanking period and by setting the noise reduction setting value according to the detected noise state. Moreover, an internal memory controller controls flicker-free conversion that doubles the vertical and horizontal direction frequencies.
FEATURES
* Memory capacity : 4.4 Mbit (960 x 288 x 16 bits) x 1 unit * Maximum input operating frequencies (16 bits/8 bits, ITU-R BT.656): 18/36 MHz (at 960 effective horizontal pixels) * Maximum output operating frequencies (normal/flicker-free): 18/36 MHz (at 960 effective horizontal pixels) * Power supply voltage : 3.3 V 0.3 V * Input pin: TTL-5V tolerant (5 V withstand voltage) * Input/output pins: Input TTL- output LVCMOS-5V tolerant (5 V withstand voltage) * Output pin: LVCMOS (3.3 V) * Input data format: YCbCr (8 bits (Y) + 8 bits (CbCr)) (4:2:2): Input 16-bit mode YCbCr (8 bits (YCbCr)) (4:2:2): Input 8-bit mode ITU-R656 (8 bits (YCbCr)): Input ITU-R BT.656 mode * Output data format: YCbCr (8 bits (Y) + 8 bits (CbCr)) (4:2:2) * Serial bus: I2C-bus interface: (400 kHz, 100 kHz) * Memory controller functions: Input: Compliant to 525/60 Hz 2:1, 625/50 Hz 2:1 Output: 625/50 Hz 2:1, 525/60 Hz 2:1, 625/100 Hz 2:1, 525/120 Hz 2:1 * Sync generator functions: Can generate sync signals of 625/50 Hz 2:1, 525/60 Hz 2:1, 625/100 Hz 2:1, 525/120 Hz 2:1. * Field-recursive type noise reduction function: Noise detection and noise subtraction type (with horizontal motion compensation) Auto mode noise reduction (noise is detected during vertical blanking period) * Package: 100 pin QFP (QFP100-P-1420-0.65-BK4)
1/13
OKI Semiconductor
x16 W_Port R_Port2 x16
BLOCK DIAGRAM
YI0-7 CI0-7 x16 R_Port1 x16 DNR YO0-7 CO0-7
x16
Input Process Block + 3D NR 3 ports Field Memory 4.4 Mbits (960 x 288 x 16)
ICLK
OCLK OE OVS OHS Memory Controller IVS_dly HREF CLKO
IVS IHS
Control Signal IHS_dly IF Output Sync. Generator INT
SCL SDA SLA1 SLA2 MODE0-2 SSG
I C-bus I/F Register
2
TEST1-5 MTEST1-7
PEDL87V2104DIGEST-01
RESET
ML87V2104
2/13
PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
PIN CONFIGURATION (TOP VIEW)
MTEST1 MTEST2 MTEST3 MTEST4 MTEST5 MTEST6 MTEST7
82
TEST1
TEST2
TEST3
TEST4
TEST5
N.C.
N.C.
N.C.
VDD
N.C.
VSS
OE
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
VDD 1 N.C. 2 N.C. 3 VSS 4 SDA 5 SCL 6 SLA1 7 SLA2 8 YI7 9 YI6 10 YI5 11 YI4 12 YI3 13 YI2 14 YI1 15 YI0 16 VDD 17 ICLK 18 VSS 19 CI7 20 CI6 21 CI5 22 CI4 23 CI3 24 CI2 25 CI1 26 CI0 27 N.C. 28 N.C. 29 VDD 30 VSS 31 IVS 32 IHS 33 MODE0 34 MODE1 35 N.C. 36 MODE2 37 CLKO 38 VDD 39 VSS 40 N.C. 41 VDD 42 DNR 43 N.C. 44 SSG 45 INT 46 OHS 47 OVS 48 HREF 49 VSS 50
81
VSS
80 79 78 77 76 75 74 73 72 71 70 69 68 67
VDD RESET N.C. N.C. N.C. N.C. N.C. VSS YO7 YO6 YO5 YO4 VDD YO3 YO2 YO1 YO0 VSS OCLK VDD CO7 CO6 CO5 CO4 VSS CO3 CO2 CO1 CO0 VDD
ML87V2104
(QFP100-P-1420-0.65-BK4)
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
3/13
PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
PIN DESCRIPTIONS
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Symbol VDD N.C. N.C. VSS SDA SCL SLA1 SLA2 YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 VDD ICLK VSS CI7 CI6 CI5 CI4 CI3 CI2 CI1 CI0 N.C. N.C. VDD VSS IVS IHS MODE0 MODE1 N.C. MODE2 CLKO VDD VSS N.C. I/O -- -- -- -- I/O I I I I I I I I I I I -- I -- I I I I I I I I -- -- -- -- I/O I/O I I -- I O -- -- -- Pad Remarks Power supply 3.3 V Unused pin Unused pin Ground Schmitt(IN)/ OpenDrain(OUT) Schmitt pull-down 50k pull-down 50k I2C-bus data pin I2C-bus clock pin Slave address setting pin Slave address setting pin Luminance signal input pin bit 7 (MSB) Luminance signal input pin bit 6 Luminance signal input pin bit 5 Luminance signal input pin bit 4 Luminance signal input pin bit 3 Luminance signal input pin bit 2 Luminance signal input pin bit 1 Luminance signal input pin bit 0 (LSB) Power supply 3.3 V Input system clock pin Ground Chrominance signal input pin bit 7 (MSB) Chrominance signal input pin bit 6 Chrominance signal input pin bit 5 Chrominance signal input pin bit 4 Chrominance signal input pin bit 3 Chrominance signal input pin bit 2 Chrominance signal input pin bit 1 Chrominance signal input pin bit 0 (LSB) Unused pin Unused pin Power supply 3.3 V Ground Input vertical sync signal input/output pin Input horizontal sync signal input/output pin Mode setting pin - bit 0 Mode setting pin - bit 1 Unused pin Mode setting pin - bit 2 Clock output (I2C-bus control possible) Power supply 3.3 V Ground Unused pin Pin Description
Schmitt(IN) pull-down 50k Schmitt(IN) pull-down 50k pull-down 50k pull-down 50k pull-down 50k
4/13
PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
No. 42 43 44 45 46
Symbol VDD DNR N.C. SSG INT
I/O -- I -- I I
Pad Remarks
pull-down 50k
pull-down 50k pull-down 50k Schmitt(IN) pull-down 50k Schmitt(IN) pull-down 50k
Pin Description Power supply 3.3 V Noise reduction output mode setting pin 0: Normal operation 1: Direct noise reduction mode Unused pin Internally generated sync signal mode setting pin Output system sync signal input/output select setting pin 0: OVS, OHS input mode 1: OVS, OHS internally generated output mode Output system horizontal sync signal input/output pin Output system vertical sync signal input/output pin Data output horizontal reference signal output pin Ground Power supply 3.3 V Chrominance signal output pin - bit 0 (LSB) Chrominance signal output pin - bit 1 Chrominance signal output pin - bit 2 Chrominance signal output pin - bit 3 Ground Chrominance signal output pin - bit 4 Chrominance signal output pin - bit 5 Chrominance signal output pin - bit 6 Chrominance signal output pin - bit 7(MSB) Ground Output system clock pin Ground Luminance signal output pin - bit 0 (LSB) Luminance signal output pin - bit 1 Luminance signal output pin - bit 2 Luminance signal output pin - bit 3 Power supply 3.3 V Luminance signal output pin - bit 4 Luminance signal output pin - bit 5 Luminance signal output pin - bit 6 Luminance signal output pin - bit 7 (MSB) Ground Unused pin Unused pin Unused pin Unused pin Unused pin System reset input pin (0 active) 0: System reset 1: Normal operation Apply ICLK cycle one and more time during "0" level after VDD voltage has reached the specified level in System reset operation.
47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78
OHS OVS HREF VSS VDD CO0 CO1 CO2 CO3 VSS CO4 CO5 CO6 CO7 VDD OCLK VSS YO0 YO1 YO2 YO3 VDD YO4 YO5 YO6 YO7 VSS N.C. N.C. N.C. N.C. N.C. RESET
I/O I/O O -- -- O O O O -- O O O O -- I -- O O O O -- O O O O -- -- -- -- -- --
79
I
5/13
PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
No. 80 81 82 83
Symbol VDD VSS MTEST7 MTEST6
I/O -- -- I I
Pad Remarks
pull-down 50k pull-down 50k
84
OE
I
pull-down 50k
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
N.C. N.C. N.C. N.C. TEST5 VDD TEST4 TEST3 TEST2 TEST1 MTEST5 MTEST4 MTEST3 MTEST2 MTEST1 VSS
-- -- -- -- I -- I I I I I I I I I --
pull-down 50k pull-down 50k pull-down 50k pull-down 50k pull-down 50k pull-down 50k pull-down 50k pull-down 50k pull-down 50k pull-down 50k
Pin Description Power supply 3.3 V Ground Memory test input pin - bit 7 (1: test mode) Memory test input pin - bit 6 (1: test mode) Output enable input pin (normally set to 1) 0: YO[7:0], CO[7:0] disable (Hi-z) 1: YO[7:0], CO[7:0] enable (drive) Equivalent operation to setting fixed to 1 in RESET=0 or DNR=1 Unused pin Unused pin Unused pin Unused pin Test input pin - bit 5 (1: test mode) Power supply 3.3 V Test input pin - bit 4 (1: test mode) Test input pin - bit 3 (1: test mode) Test input pin - bit 2 (1: test mode) Test input pin - bit 1 (1: test mode) Memory test input pin - bit 5 (1: test mode) Memory test input pin - bit 4 (1: test mode) Memory test input pin - bit 3 (1: test mode) Memory test input pin - bit 2 (1: test mode) Memory test input pin - bit 1 (1: test mode) Ground
Notes: In 8-bit YcbCr and ITU-R BT. 656 mode, CI0-7 pin should be connected to the Vss level.
6/13
PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Power supply voltage Input pin voltage Output pin short-circuit current Power dissipation Operating temperature Storage temperature Symbol VDD VI IOS PD Topr Tstg Condition Ta = 25C Ta = 25C Ta = 25C Ta = 25C -- -- Rating -0.3 to 4.6 -0.3 to 7.0 50 1 0 to 70 -50 to 150 Unit V V mA W C C
Recommended Operating Conditions
Parameter Power supply voltage Power supply voltage Operating temperature Symbol VDD VSS Ta Min. 3.0 0 0 Typ. 3.3 0 -- Max. 3.6 0 70 Unit V V C
Pin Capacitance
(VCC = 3.3 V 0.3 V, f = 1 MHz, Ta = 25C) Parameter Input capacitance Input/output capacitance (IVS, IHS, OVS, OHS) Input/output capacitance (SDA) Output capacitance Symbol Ci Cio1 Cio2 Co Min. -- -- -- -- Max. 10 10 10 10 Unit pF pF pF pF
7/13
PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
DC Characteristics
(Ta = 0 to 70C) Parameter H level input voltage L level input voltage Schmitt trigger threshold voltage (SDA, SCL, IVS, IHS, OVS, OHS) Schmitt trigger threshold voltage (SDA, SCL, IVS, IHS, OVS, OHS) Hysteresis voltage width H level input current (pull-down) Input leakage current H level output voltage (other than SDA) L level output voltage (other than SDA) L level output voltage (N-Ch.OD) (SDA) Output leakage current Symbol VIH VIL Vt+ Vt- Vh IIH IIL VOH VOL VOOL IOL Condition -- -- -- -- -- 50 k Pull Down TTL IOH = -4 mA IOL = 4 mA IOL = 4 mA 0 Vout VDD Output is disabled ICLK: 36 MHz Supply current (during operation) Supply current (during standby) IDD1 IDD2 OCLK: 36 MHz Output open Input pin = VIL -- 10 mA -- 100 mA Min. 2.0 -0.3 -- 0.8 0.1 20 -10 2.2 0 0 -10 Max. 5.5 0.8 2.0 -- -- 200 10 VDD 0.4 0.4 10 Unit V V V V V A A V V V A
AC Characteristics
(Ta = 0 to 70C) Parameter ICLK clock cycle time ICLK clock cycle time ICLK clock duty ratio ICLK system input set-up time ICLK system input hold time ICLK system output delay time OCLK clock cycle time OCLK clock duty ratio OCLK system input set-up time OCLK system input hold time OCLK system output delay time CLKO delay time Data through time Symbol tICLK tICLK dtICLK tIISU tIIH tIOD tOCLK dtOCLK tOISU tOIH tOOD tCKD tDIDO Condition Input 16-bit mode Input 8-bit mode -- -- -- CL = 20 pF -- -- -- -- CL = 20 pF CL = 20 pF (OCLK output) CL = 20 pF (IICLK output) CL = 20 pF (ICLK output) CL = 20 pF Min. 54 27 45 5 3 5 27 45 5 3 5 5 6 6 3 Max. -- -- 55 -- -- 22 -- 55 -- -- 22 22 25 22 20 ns ns Unit Ns Ns % ns ns ns ns % ns ns ns
Notes: 1. Input signal reference levels for the parameter measurement are VIH = 3.0 V and VIL = 0 V. Output reference levels are VOH = 1.5 V and VOL = 1.5 V.
8/13
PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
Notes: 2. On power-up, the device is designed to begin proper operation after at least 100 s after VCC has stabilized to a value within the range of recommended operating conditions. After this 100 s stabilization interval, a minimum of 1-field dummy write operations and read operations must be performed.
9/13
PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
Application Example1 Mode setting: ALL Pin Open Slave address: 1011100 Input format: 16bit YcbCr (Register setting: DISEL=0,R656=0)
3.3V
I2C-bus MATER CONTROLLER
VDD SDA SCL OE 84
VIDEO IN
DEGITAL VIDEO DECODER
YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 CI7 CI6 CI5 CI4 CI3 CI2 CI1 CI0 IVS IHS
1,17,30, 39,51,61 , 68,80,90
5 6
9 10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 32 33
NR-FIFO ML87V2104
72 71 70 69 67 66 65 64 60 59 58 57 55 54 53 52 49 48 47 38
YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0 CO7 CO6 CO5 CO4 CO3 CO2 CO1 CO0 HREF OVS OHS CLKO
RGB CONVERTER DEFLECTION / SCAN CONVERTER / MPEG ENCODER
DATA OUT
CLK RESET
ICLK
18
4,19,31, 40,50,56, 63,73,81, 100
79
RESET
GND
System Reset
Application Example2 Mode setting: DNR=1(Direct Noise Reduction Mode), Others Pin:OPEN Slave address: 1011100 Input format: ITU-R BT.656(Register setting: DISEL=0,R656=1) Output format: ITU-R BT.656(Register setting: DOSEL=1)
3.3V
I2C-bus MATER CONTROLLER ITU-R BT.656 Format
YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 CI7 CI6 CI5 CI4 CI3 CI2 CI1 CI0 9 10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 OPEN OPEN 32 33 4,19,31, 40,50,56, 63,73,81, 100 VDD DNR OE SDA SCL
OCLK
CX
62
1,17,30, 39,51,61 , 68,80,90
43 84
5 6
ITU-R BT.656 Format
72 71 70 69 67 66 65 64 60 59 58 57 55 54 53 52 49 48 47 38 YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0 OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN
VIDEO IN
DEGITAL VIDEO DECODER
NR-FIFO ML87V2104
RGB CONVERTER DEFLECTION / SCAN CONVERTER / MPEG ENCODER
DATA OUT
RESET
System Reset
OCLK
GND
CLK
18
RESET
ICLK
79
62
10/13
PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
PACKAGE DIMENSIONS
(Unit: mm)
QFP100-P-1420-0.65-BK4
Mirror finish
5
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 1.54 TYP. 4/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package
The QFP is a surface mount type package, which is very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
11/13
PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
REVISION HISTORY
Document No.
PEDL87V2104DIGEST-01
Date
Jan.20. 2003
Page Previous Current Edition Edition
Description
Preliminary edition 1
12/13
PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd.
3.
4.
5.
6.
7.
8.
13/13

▲Up To Search▲

Price & Availability of ML87V2104

	To Download ML87V2104 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .